1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to a method of manufacturing a semiconductor device having a size equal to or larger than the field size of exposure equipment used in a semiconductor device manufacturing process.
2. Related Background Art
An image pickup element for a digital camera or an X-ray radiographing image pickup element, a large scale system LSI, a long sensor used for a scanner, or the like, a heater board of a long head used in a printing head of a bubble jet system, and the like, are severally formed larger in device size than those of ordinary ones. Sometimes, a semiconductor device (hereinafter sometimes referred to as a “chip”), having a size equal to or larger than the field size or the exposure equipment is frequently needed. The chip having the size equal to or larger than the field size of the exposure equipment is generally manufactured by the so-called divided exposure process, in which the chip is divided into a plurality of areas, and exposure is performed by being divided into a plurality of times using a plurality of masks corresponding to the respective areas.
However, there is a case wherein a “difference” is generated at a joining part of patterns at boundary parts between each area at which the divided exposure is performed in a semiconductor device manufactured by the divided exposure processes. The “difference” means the differences in position, shape and size between a pattern formed in a certain area in which the divided exposure has been performed and a pattern formed on an area adjoining the area. The difference is hereinafter referred to as a “pattern difference”. For suppressing the dispersion of the characteristics of a semiconductor device caused by the pattern difference, it is necessary to design mask patterns in anticipation of the components of the pattern difference. At that time, it is also necessary to anticipate the dispersion of the manufacturing processes. However, there is a problem in which a chip design of a fine pattern fully utilizing the intrinsic performance of the exposure equipment is limited, because the design rule of the whole chip must be loosed in the case of performing such a mask pattern design.
Moreover, when an image is photographed using a solid state image pickup element having a positional different or dimensional difference on both the sides of the boundary part of each area having received divided exposure, stripe-like image unevenness is sometimes generated at the boundary part. The generation of the stripe-like image unevenness means that the amounts of light entering a light receiving portion of a photoelectric conversion element, or the read amounts of photoelectrically converted electrical charges differ from each other on both sides of the boundary part. It is conceivable that the difference of the amount of light entering the light receiving portion of the photoelectric conversion element is generated by the differences of relative positional relations between the light receiving portion, the light shielding film, color film, micro lens, and the like, of the photoelectric conversion element. Moreover, it is conceivable that the difference of the read amounts of electrical charges is caused by the difference of the read voltage components by capacity division, on both sides of the boundary part, and it is also conceivable that the difference of positional relations of the electrodes constituting the capacity.
Accordingly, it is necessary to make the dispersion of every alignment and process of each area receiving divided exposure smaller, as much as possible, in a divided exposure process. Japanese Patent Application Laid-Open No. 2004-153120 and Japanese Patent Application Laid-Open No. 2004-153131 disclose a technology of reducing the dispersion of the alignment and the process of each area receiving the divided exposure. However, because it is impossible to remove alignment errors and the dispersion of processes completely, it is realistic to introduce the design increasing margins for the alignment errors and the dispersion of every process. U.S. Published Patent Application No. 2004/0105022 A1 (Japanese Patent Application Laid-Open No. 2004-111867), Japanese Patent application Laid-Open No. 2004-111867), Japanese Patent Application Laid-Open No. 2004-111871, U.S. Published Patent Application No. 2004/0070039 A1 (Japanese Patent Application Laid-Open No. 2004-134524) disclose technologies for increasing the margins to the alignment errors, and the dispersion of every process.
Moreover, Japanese Patent Application Laid-Open No. 2002-110511 describes the setting of a focus offset value to each shot of joining exposure. U.S. Pat. No. 6,506,544 (Japanese Patent Application Laid-Open No. 2000-199973) describes the use of a common pattern and a not common pattern as a pattern formed on a reticle used for divided exposure. Japanese Patent Application Laid-Open No. 2003-151880 describes the regulation of a field diaphragm, a slit width, and the like, in a joining part at the time of duplicate exposure. However, none of the disclosed contents proposes improvement means to the aberration characteristic owned by the exposure equipment essentially.
It is anticipated that it becomes necessary to make the pattern difference smaller as the miniaturization of a line width further progresses in the future. Then, it is desired to make the pattern difference smaller, based on the individual technologies or the technology combining the individual technologies disclosed in the patent documents mentioned above.
It is an object of the present invention to solve the various problems caused by the pattern difference in a semiconductor device manufactured by divided exposure by making the pattern difference smaller, as much as possible, or by adjusting the generation position of the pattern difference.